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6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 1 6 bit 3 8 4 channel rsds tft-lcd source driver august . 1999. ver. 0. 0 prepared by: akira kang akira211@samsung. c o.kr S6C0666
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 2 S6C0666 specification revision history version content date 0.0 original aug . 1999
6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 3 contents introduction ................................ ................................ ................................ ................................ ................. 4 features ................................ ................................ ................................ ................................ ......................... 4 block diagram ................................ ................................ ................................ ................................ .............. 5 pin assingments ................................ ................................ ................................ ................................ ............ 6 pin descriptions ................................ ................................ ................................ ................................ ........... 7 operation description ................................ ................................ ................................ ............................... 8 rsds receiver and demux ................................ ................................ ................................ ...................... 8 rsds data bus interface control ................................ ................................ ................................ ...... 8 display data transfer ................................ ................................ ................................ ............................ 8 extension of output ................................ ................................ ................................ ............................... 8 relationship between input data value and output voltage ................................ .................. 8 absolute maximum ratings ................................ ................................ ................................ .................... 15 recommended operation conditions ................................ ................................ ................................ .. 15 dc characteristics ................................ ................................ ................................ ................................ ... 16 rsds characteristics ................................ ................................ ................................ .............................. 17 ac characteristics ................................ ................................ ................................ ................................ ... 18 waveforms ................................ ................................ ................................ ................................ ................... 19 rsds data timing diagram ................................ ................................ ................................ ....................... 20
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 4 introduction the S6C0666 is a source driver suitable for reduced swing differential signaling (rsds) digital interface. it converts 18-bit digital data into the analog voltage for 384 channels, charging each sub-pixel to the correct gray level corresponding to the digital value. the rsds path to the panel timing controller contributes toward lowering radiated emi, reducing system power consumption and eliminates one of the two pixel busses used in typical xga, sxga tft lcd panels. this single 9-bit differential bus conveys the 18-bit color data for xga, sxga panels. features tft active matrix lcd source driver lsi 64 g/s is possible through 10 (5 by 2) external power supply and d/a converter both dot inversion display and n - line inversion display are possible compatible with gamma-correction logic supply voltage: 2. 7 to 3.6 v lcd driver supply voltage: 7. 0 to 10.5 v output dynamic range: 6 . 8 to 10.3 vp-p maximum operating frequency: fmax = 65 mhz (internal data transmission rate at 2.7 v operation) o utput: 384 outputs reduced swing differential signaling (rsds) digital interface for low power consumption and low emi. minimum rsds input swing level (clkn, clkp, datan, datap): 100mv data bus interface control pin (datpol) tcp or cof available
6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 5 block diagram output buffer r-dac data latches 128 bit shift register pol vgma1 to vgma10 data register clk1 rsds receiver d00p d00n d01p d01n d22p d22n clkp clkn shl 6 6 6 6 6 6 dio1 dio2 line repair amp rpi2 rpi1 rpo2 rpo1 6 6 6 6 6 6 y1 y2 y3 y382 y383 y384 figure 1. S6C0666 block diagram
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 6 pin assingments rpi1 rpo1 dio1 d00n d00p d01n d01p d02n d02p y1 y2 y3 y4 y5 y6 y7 y8 y10 y11 y12 y372 y373 y374 y375 y376 y377 y378 y379 y380 y381 y382 y383 y384 y9 pol clk1 clkn clkp vss1 vgma1 vgma2 vgma3 vgma4 vgma5 vss2 vdd2 vgma6 vgma7 vgma8 vgma9 vgma10 shl vdd1 d10n d10p d11n d11p d12n d12p d20n d20p d21n d21p d22n d22p dio2 rpo2 rpi2 datpol S6C0666 output 384 input 44 figure 2. S6C0666 pin assignments
6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 7 pin descriptions symbol pin name description vdd1 logic power supply 2. 7 to 3.6 v vdd2 driver power supply 7 . 0 to 10 . 5 v vss1 logic ground ground (0 v) vss2 driver ground ground (0 v) y1 to y 384 driver outputs the d/a converted 6 4 gray-scale analog voltage is output. d0p<0:2> d0n<0:2> d1p<0:2> d1n<0:2> d2p<0:2> d2n<0:2> rsds data input total data lines consist of 18 data bus. (6-bit digital, 3 colors (r, g, b) and 2 differential input pairs) the 3 - bit differential input pairs generate the internal 6 - bit data through the comparison between dxxp and dxxn. shl shift direction control input this pin controls the direction of shift register in cascade connection. when shl = h: dio1 input, y1 ? y 384 , dio2 output when shl = l: dio2 input, y 384 ? y1, dio1 output dio1 start pulse input / output shl = h: used as the start pulse input pin. shl = l: used as the start pulse output pin. dio2 start pulse input / output shl = h: used as the start pulse output pin. shl = l: used as the start pulse input pin. datpol data inversion input datpol = l: no inversion datpol = h: data polarity inversion (h ? l) pol polarity input pol = h: the reference voltage for odd number outputs are vgma 1 to vgma 5 and those for even number outputs are vgma 6 to vgma 10 . pol = l: the reference voltage for odd number outputs are vgma 6 to vgma 10 and those for even number outputs are vgma 1 to vgma 5 . clk p clkn rsds s hift clock input the rsds clock input pairs generate the internal shift clock, clk2, through the comparison between clkp and clkn. clk1 latch input S6C0666 clears 128 shift registers at the rising edge of clk1 and outputs the analog data to the each channel at the falling edge. vgma1 to vgma1 0 gamma corrected power supplies input the gamma corrected power supplies from external source. vdd2 > vgma1 > vgma2 > ?? > vgma 9 > vgma 10 > vss2 keep power suppl ies unchanged during the gray-scale voltage output. rpi1, rpo1 rpi2, rpo2 line-repair amp input / output the structure of the line-repair amp is the same as that of the analog output. rpi1 (rpi2) ? impedance changed ? rpo1 (rpo2) test test input test = l: normal operation mode test = h: test mode (op amp cut-off, rpd = 1 5 k w )
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 8 operation description rsds receiver and demux the S6C0666 adapts the rsds interface for emi solution. the internal rsds receiver block operates the comparison between the transmitted differential input pair data. the input data lines from the timing controller to the rsds receiver consist of 6-bit digital, 3 colors, 1 port, 2 differential pairs ( dxxp / dxxn). the input common mode voltage range at the rsds receiver is 1.2 v. the differential data and clock signals from the panel timing controller arrive at the S6C0666 as multiplexed, even and odd data fields. (i.e., the data is 2:1 multiplexed). the nominal peak to peak swing of this data is 200 mv across a termination resistor. rsds data bus interface control datpol controls the internal data inversion. when datpol = ? h ? , the internal data is inverted. the inverted data is the same that the rsds receiver operates the comparison between the cross-transmitted differential input pair data. using the data inversion input pin, datpol, the rsds data bus interface can be changed. display data transfer when dio1 (or dio2) pulse is loaded into the internal latch on the falling edge of clkp, dio1 (or dio2) pulse enables the operation of data transfer, so display data is valid on the 2nd falling edge of clkp. once all the data of 384 channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though clkp is provided until next dio1 (or dio2) input. when next dio1 (or dio2) is provided, new display data is valid on the 2nd falling edge of clkp after the rising edge of dio1 (or dio2). extension of output output pin can be adjusted to an extended screen by cascade connection. when shl = "l", connect dio1 pin of the previous stage to the dio2 pin of the next stage and all the input pins except dio1 and dio2 are connected together in each device. when shl = "h", connect dio2 pin of the previous stage to the dio1 pin of the next stage and all the input pins except dio2 and dio1 are connected together in each device. relationship between input data value and output voltage the lcd drive output voltages are determined by the input data and 10 (5 by 2) gamma corrected power supplies (vgma1 to vgma10). besides, to be able to deal with dot line inversion when mounted on a single- side, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. among 5 by 2 gamma corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective 5 gamma corrected voltages of vgma1 to vgma5 and vgma6 to vgma10.
6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 9 vcom input data vgma1 vgma2 vgma3 vgma4 vgma5 vgma10 00h 08h 10h 18h 20h 28h 30h 38h 3fh vss2 vdd2 vgma9 vgma8 vgma6 vgma7 figure 3. gamma correction curve
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 10 table 1. resistor strings (r0 to r62, unit: w ) name value name value name value name value r0 500 r16 330 r32 175 r48 21 0 r1 500 r17 330 r33 175 r49 220 r2 500 r18 330 r34 1 70 r50 230 r3 500 r19 320 r35 1 70 r 51 24 0 r4 500 r20 300 r36 165 r52 250 r5 500 r21 280 r37 165 r53 260 r6 500 r22 270 r38 165 r54 27 0 r7 500 r23 260 r39 165 r55 290 r8 500 r24 250 r40 17 0 r56 300 r9 500 r25 240 r41 1 70 r57 310 r10 500 r26 230 r42 1 70 r58 320 r11 500 r27 220 r43 1 7 5 r59 340 r12 450 r28 210 r44 175 r60 340 r13 450 r29 200 r45 175 r61 340 r14 400 r30 190 r46 180 r62 340 r15 370 r31 180 r47 200
6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 11 table 2. relationship between input data and output voltage value input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03 h 04h 05 h 06 h 07h 0 0 0 1 1 1 vh0 vh1 vh2 vh 3 vh4 vh 5 vh 6 vh7 vgma1 vgma1+(vgma2 - vgma1) 500/7670 vgma1+(vgma2-vgma1) 1000/7670 vgma1+(vgma2-vgma1) 1500/7670 vgma1+(vgma2-vgma1) 2000/7670 vgma1+(vgma2-vgma1) 2500/7670 vgma1+(vgma2-vgma1) 3000/7670 vgma1+(vgma2-vgma1) 3500/7670 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08 h 09h 0a h 0b h 0ch 0d h 0e h 0fh 0 0 1 1 1 1 vh 8 vh9 vh 1 0 vh 1 1 vh12 vh 13 vh 1 4 vh15 vgma1+(vgma2-vgma1) 4000/7670 vgma1+(vgma2-vgma1) 4500/7670 vgma1+(vgma2-vgma1) 5000/7670 vgma1+(vgma2-vgma1) 5500/7670 vgma1+(vgma2-vgma1) 6000/7670 vgma1+(vgma2-vgma1) 6450/7670 vgma1+(vgma2-vgma1) 6900/7670 vgma1+(vgma2-vgma1) 7300/7670 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10 h 11h 12 h 13 h 14h 15 h 16 h 17h 0 1 0 1 1 1 vh 16 vh17 vh 18 vh 19 vh20 vh2 1 vh2 2 vh23 vgma2 vgma2+(vgma3-vgma2) 330/4140 vgma2+(vgma3-vgma2) 660/4140 vgma2+(vgma3-vgma2) 990/4140 vgma2+(vgma3-vgma2) 1310/4140 vgma2+(vgma3-vgma2) 1610/4140 vgma2+(vgma3-vgma2) 1890/4140 vgma2+(vgma3-vgma2) 2160/4140 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18 h 19h 1a h 1bh 1c h 1d h 1e h 1fh 0 1 1 1 1 1 vh24 vh25 vh2 6 vh27 vh2 8 vh2 9 vh 30 vh31 vgma2+(vgma3-vgma2) 2420/4140 vgma2+(vgma3-vgma2) 2670/4140 vgma2+(vgma3-vgma2) 2910/4140 vgma2+(vgma3-vgma2) 3140/4140 vgma2+(vgma3-vgma2) 3360/4140 vgma2+(vgma3-vgma2) 3570/4140 vgma2+(vgma3-vgma2) 3770/4140 vgma2+(vgma3-vgma2) 3960/4140 note: vdd2 > vgma1 > vgma2 > vgma3 > vgma4 > vgma5
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 12 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 2 0h 21h 22h 23 h 24h 25 h 26 h 27h 1 0 0 1 1 1 vh 32 vh33 vh34 vh 35 vh36 vh 37 vh 38 vh39 vgma3 vgma3+(vgma4-vgma3) 175/2765 vgma3+(vgma4-vgma3) 350/2765 vgma3+(vgma4-vgma3) 520/2765 vgma3+(vgma4-vgma3) 690/2765 vgma3+(vgma4-vgma3) 855/2765 vgma3+(vgma4-vgma3) 1020/2765 vgma3+(vgma4-vgma3) 1185/2765 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28 h 29h 2a h 2b h 2ch 2d h 2e h 2fh 1 0 1 1 1 1 vh 40 vh41 vh 42 vh 43 vh44 vh 45 vh 46 vh47 vgma3+(vgma4-vgma3) 1350/2765 vgma3+(vgma4-vgma3) 1520/2765 vgma3+(vgma4-vgma3) 1690/2765 vgma3+(vgma4-vgma3) 1860/2765 vgma3+(vgma4-vgma3) 2035/2765 vgma3+(vgma4-vgma3) 2210/2765 vgma3+(vgma4-vgma3) 2385/2765 vgma3+(vgma4-vgma3) 2565/2765 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30 h 31h 32 h 33 h 34h 35 h 36 h 37h 1 1 0 1 1 1 vh 48 vh49 vh 50 vh 51 vh52 vh53 vh54 vh55 vgma4 vgma4+(vgma5-vgma4) 210/4260 vgma4+(vgma5-vgma4) 430/4260 vgma4+(vgma5-vgma4) 660/4260 vgma4+(vgma5-vgma4) 900/4260 vgma4+(vgma5-vgma4) 1150/4260 vgma4+(vgma5-vgma4) 1410/4260 vgma4+(vgma5-vgma4) 1680/4260 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38 h 39h 3a h 3bh 3c h 3d h 3e h 3fh 1 1 1 1 1 1 vh56 vh57 vh58 vh59 vh60 vh61 vh 62 vh63 vgma4+(vgma5-vgma4) 1970/4260 vgma4+(vgma5-vgma4) 2270/4260 vgma4+(vgma5-vgma4) 2580/4260 vgma4+(vgma5-vgma4) 2900/4260 vgma4+(vgma5-vgma4) 3240/4260 vgma4+(vgma5-vgma4) 3580/4260 vgma4+(vgma5-vgma4) 3920/4260 vgma5
6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 13 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03 h 04h 05 h 06 h 07h 0 0 0 1 1 1 vl0 vl1 vl2 vl 3 vl4 vl 5 vl 6 vl7 vgma1 0 vgma10+(vgma9-vgma10) 500/7670 vgma10+(vgma9-vgma10) 1000/7670 vgma10+(vgma9-vgma10) 1500/7670 vgma10+(vgma9-vgma10) 2000/7670 vgma10+(vgma9-vgma10) 2500/7670 vgma10+(vgma9-vgma10) 3000/7670 vgma10+(vgma9-vgma10) 3500/7670 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08 h 09h 0a h 0b h 0ch 0d h 0e h 0fh 0 0 1 1 1 1 vl 8 vl9 vl 1 0 vl 1 1 vl12 vl 13 vl 1 4 vl15 vgma10+(vgma9-vgma10) 4000/7670 vgma10+(vgma9-vgma10) 4500/7670 vgma10+(vgma9-vgma10) 5000/7670 vgma10+(vgma9-vgma10) 5500/7670 vgma10+(vgma9-vgma10) 6000/7670 vgma10+(vgma9-vgma10) 6450/7670 vgma10+(vgma9-vgma10) 6900/7670 vgma10+(vgma9-vgma10) 7300/7670 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10 h 11h 12 h 13 h 14h 15 h 16 h 17h 0 1 0 1 1 1 vl 16 vl17 vl 18 vl 19 vl20 vl2 1 vl2 2 vl23 vgma9 vgma9+(vgma8-vgma9) 330/4140 vgma9+(vgma8-vgma9) 660/4140 vgma9+(vgma8-vgma9) 990/4140 vgma9+(vgma8-vgma9) 1310/4140 vgma9+(vgma8-vgma9) 1610/4140 vgma9+(vgma8-vgma9) 1890/4140 vgma9+(vgma8-vgma9) 2160/4140 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18 h 19h 1a h 1bh 1c h 1d h 1e h 1fh 0 1 1 1 1 1 vl24 vl25 vl2 6 vl27 vl2 8 vl2 9 vl 30 vl31 vgma9+(vgma8-vgma9) 2420/4140 vgma9+(vgma8-vgma9) 2670/4140 vgma9+(vgma8-vgma9) 2910/4140 vgma9+(vgma8-vgma9) 3140/4140 vgma9+(vgma8-vgma9) 3360/4140 vgma9+(vgma8-vgma9) 3570/4140 vgma9+(vgma8-vgma9) 3770/4140 vgma9+(vgma8-vgma9) 3960/4140 note: vgma6 > vgma7 > vgma8 > vgma9 > vgma10 > vss2
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 14 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 2 0h 21h 22h 23 h 24h 25 h 26 h 27h 1 0 0 1 1 1 vl 32 vl33 vl34 vl 35 vl36 vl 37 vl 38 vl39 vgma 8 vgma8+(vgma7-vgma8) 175/2765 vgma8+(vgma7-vgma8) 350/2765 vgma8+(vgma7-vgma8) 520/2765 vgma8+(vgma7-vgma8) 690/2765 vgma8+(vgma7-vgma8) 855/2765 vgma8+(vgma7-vgma8) 1020/2765 vgma8+(vgma7-vgma8) 1185/2765 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28 h 29h 2a h 2b h 2ch 2d h 2e h 2fh 1 0 1 1 1 1 vl 40 vl41 vl 42 vl 43 vl44 vl 45 vl 46 vl47 vgma8+(vgma7-vgma8) 1350/2765 vgma8+(vgma7-vgma8) 1520/2765 vgma8+(vgma7-vgma8) 1690/2765 vgma8+(vgma7-vgma8) 1860/2765 vgma8+(vgma7-vgma8) 2035/2765 vgma8+(vgma7-vgma8) 2210/2765 vgma8+(vgma7-vgma8) 2385/2765 vgma8+(vgma7-vgma8) 2565/2765 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30 h 31h 32 h 33 h 34h 35 h 36 h 37h 1 1 0 1 1 1 vl 48 vl49 vl 50 vl 51 vl52 vl53 vl54 vl55 vgma7 vgma7+(vgma6-vgma7) 210/4260 vgma7+(vgma6-vgma7) 430/4260 vgma7+(vgma6-vgma7) 660/4260 vgma7+(vgma6-vgma7) 900/4260 vgma7+(vgma6-vgma7) 1150/4260 vgma7+(vgma6-vgma7) 1410/4260 vgma7+(vgma6-vgma7) 1680/4260 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38 h 39h 3a h 3bh 3c h 3d h 3e h 3fh 1 1 1 1 1 1 vl56 vl57 vl58 vl59 vl60 vl61 vl 62 vl63 vgma7+(vgma6-vgma7) 1970/4260 vgma7+(vgma6-vgma7) 2270/4260 vgma7+(vgma6-vgma7) 2580/4260 vgma7+(vgma6-vgma7) 2900/4260 vgma7+(vgma6-vgma7) 3240/4260 vgma7+(vgma6-vgma7) 3580/4260 vgma7+(vgma6-vgma7) 3920/4260 vgma6
6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 15 absolute maximum ratings t able 3. absolute maximum ratings (vss1 = vss2 = 0 v) parameter symbol ratings unit logic supply voltage vdd1 -0.3 to 5.0 v driver supply voltage vdd2 -0.3 to 1 2.0 v vgma1 to 1 0 -0.3 to vdd2 + 0.3 rpi1, rpi2 -0.3 to vdd2 + 0.3 input voltage others -0.3 to vdd1 + 0.3 v dio1, dio 2 -0.3 to vdd1 + 0.3 y1 to y 384 -0.3 to vdd2 + 0.3 output voltage rpo1, rpo2 -0.3 to vdd2 + 0.3 v operating power dissipation pd 15 0 mw operation temperature top -20 to 75 c storage temperature tstg -55 to 1 25 c cautions: if lsis are stressed beyond those listed above ? absolute maximum ratings ? , they may be permanently destroyed. these are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. turn on power order: vdd1 ? control signal input ? vdd2 ? vgma1 to vgma10 turn off power order: vgma1 to vgma10 ? vdd2 ? control signal input ? vdd1 recommended operation condition s table 4. recommended operation conditions ( ta = - 20 to 70 c , vss1 = vss2 = 0 v) parameter symbol min. typ. max. unit logic supply voltage vdd1 2.7 3.0 3.6 v driver supply voltage vdd2 7 . 0 - 1 0 . 5 v vgma1 to vgma 5 0.5vdd2 - vdd2 - 0.1 v gamma corrected voltage vgma 6 to vgma1 0 + 0.1 - 0.5vdd2 v driver part output voltage vyo + 0.1 - vdd2 - 0.1 v vdd1 = 2.7v - - 65 maximum clock frequency fmax vdd1 = 3.0v - - 75 mhz output load capacitance cl - - 15 0 pf / pin
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 16 dc characteristics table 5 . dc characteristics ( ta = -20 to 75 c, vdd1 = 2. 7 to 3.6 v, vdd2 = 7. 0 to 10.5 v, vss1 = vss2 = 0) parameter symbol condition min. typ. max. unit high level input voltage vih 0. 7 vdd1 - vdd1 low level input voltage vil 0 - 0. 3 vdd1 v input leak age current il 1 shl, clk 1 , pol, dio1 (dio2) - 1 - 1 repair input leak current il2 rpi1(rpi2) - 1 - 1 m a high level output voltage voh dio1(dio2), io = - 1.0 ma vdd1 - 0.5 - - low level output voltage vol dio1(dio2), io = + 1.0 ma - - 0.5 v resistance between gamma voltage r0 to r 62 refer to table 1. resistor strings rn 0.7 rn 1.3 w ivoh 1 vdd2 = 8 .0 v, vx (1) = 4 . 0 v, vyo (2) = 7.0 v - - 0.8 - 0.4 driver output current ivol 1 vdd2 = 8 .0 v, vx (1) = 4 . 0 v, vyo (2) = 1 . 0 v 0.4 0.8 - ivoh2 vdd2 = 8 .0 v, vx (1) = 4 . 0 v, vyo (2) = 7.0 v - - 2 .0 -1. 0 line-repair driver output current ivol2 vdd2 = 8 .0 v, vx (1) = 4 . 0 v, vyo (2) = 1 . 0 v 1. 0 2 .0 - ma output voltage deviation d vo input data: 00h to 3fh - 10 20 output swing voltage difference deviation dvrms (3) input data: 00h to 3fh - 5 15 mv output voltage range v yo input data: 00h to 3 fh vss2 + 0.1 - vdd2 - 0.1 v logic part dynamic current idd1 vdd1 = 3.0 v (4) - 6 .0 8.0 driver part dynamic current idd2 vdd 1 = 3.0 v, vdd2 = 9.0 v , vgma1 = 8.5 v, vgma5 = 5.0 v, vgma6 = 4.0 v, vgma10 = 0.5 v (4) (5) - 6 .0 9 .0 ma notes: 1. vx is the voltage applied to analog output pins y1 to y384. 2. vyo is the output voltage of analog output pins y1 to y384. 3. dvrms = max. deviation of ( vhx-vlx) vhx; the x gray level positive polarity driver output voltage vlx; the x gray level negative polarity driver output voltage 4. clk1 period = 20 m s at fclkp = 33 mhz, data pattern = 1010 ?? , (checkerboard pattern), ta = 25 c 5. yout load condition (refer to figure 4. yout load condition) applied.
6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 17 rsds characteristics table 6 . rsds characteristics ( ta = - 20 to 75 c, vdd1 = 2. 7 to 3.6 v, vdd2 = 7. 0 to 10.5 v, vss1 = vss2 = 0) parameter symbol condition min. typ. max. unit rsds high input voltage vih rsds vcm rsds = + 1.2 v (1) 100 200 rsds low input voltage vih rsds vcm rsds = + 1.2 v (1) - 200 - 100 mv rsds common mode input voltage range vcm rsds vdiff rsds = + 200 mv ( 2 ) vss1 + 0.1 - vdd1 - 1.5 v rsds input leakage current idl dxxp, dxxn, clkp, clkn - 10 - 10 m a notes: 1. vcm rsds = (vclkp + vclkn) / 2 or vcm rsds = ( vdxxp + vdxxn) / 2 2. vdiff rsds = vclkp - vclkn or vdiff rsds = vdxxp - vdxxn vcom=0.5vdd2 10k w 20k w 20k w 20pf 20pf 20pf yout figure 4. yout load condition
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 18 ac characteristics table 6. ac characteristics ( ta = - 20 to 75 c, v dd2 = 7.0 to 10.5 v, v ss1 = vss2 = 0 v) p arameter s ymbol c ondition min. typ. m ax . u nit clock pulse width pwclk - 1 5 - - clock pulse low period pwclk(l) - 6 - - clock pulse high period pwclk(h) - 6 - - data setup time tsetup1 - 2 - - data hold time thold1 - 0 - - start pulse setup time tsetup2 - 4 - - start pulse hold time thold2 - 2 - - start pulse delay time tplh1 cl = 15 pf - - 1 2 ns dio signal pulse width pwdio 1clkp - 2clkp clk1 setup time tsetup3 - 2clkp - - clk p period clk1 high pulse width pwclk1 - 5clkp - 2 driver output delay time1 tphl1 (1) (3) - - 6 driver output delay time2 tphl2 ( 2 ) (3) - 10 repair output delay time1 tphl3 cl = 150pf - - 6 repair output delay time2 tphl4 cl = 150pf - 10 m s last data timing tldt - 1 clkp - - clkp period clk1-clk2 time tclk1-clk2 clk1 - ? clk p 4 - - pol-clk1 time tpol-clk1 pol - or ? clk1 - 14 - - clk1 -pol time tclk1 -pol clk1 ? pol - or 10 - - ns notes: 1. the value is specified when the drive voltage value reaches the target output voltage level of 90% 2. the value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy. 3. yout load condition (refer to figure 4. yout load condition)
6 bit 384 channel rsds tft ? lcd source driver premilinary ver 1.0 S6C0666 19 waveforms clkp-clkn (rsds) input dio1; shl=h dio2; shl=l dxxp-dxxn (rsds) even odd even odd 1st data 2nd data invalid output dio1; shl=h dio2; shl=l tsetup2 vihrsds 0v vilrsds thold2 90% clkp-clkn vihrsds 0v vilrsds vihrsds 0v vilrsds tsetup1 tsetup1 thold1 thold1 clkp-clkn dxxp-dxxn input dio1; shl=h dio2; shl=l clk1 pol y1 to y384 pwdio rpo1, rpo2 odd even odd even odd even tplh1 tphl1 90% 10% tclk1-clk2 90% 10% 10% 90% tpol-clk1 tldt pwclk1 tphl1 tphl2 tphl3 tphl4 tclk1-pol 10% 90% 10% 90% invalid 90% 90% pwclk(l) pwclk(h) pwclk 90% figure 5. waveforms
S6C0666 premilinary ver 1.0 6 bit 384 channel rsds tft ? lcd source driver 20 rsds data timing diagram b[0] 1 b[1] 1 b[0] 2 b[1] 2 b[0] 3 b[1] 3 b[0] 4 b[1] 4 b[2] 1 b[3] 1 b[2] 2 b[3] 2 b[2] 3 b[3] 3 b[2] 4 b[3] 4 b[4] 1 b[5] 1 b[4] 2 b[5] 2 b[4] 3 b[5] 3 b[4] 4 b[5] 4 g[0] 1 g[1] 1 g[0] 2 g[1] 2 g[0] 3 g[1] 3 g[0] 4 g[1] 4 g[2] 1 g[3] 1 g[2] 2 g[3] 2 g[2] 3 g[3] 3 g[2] 4 g[3] 4 g[4] 1 g[5] 1 g[4] 2 g[5] 2 g[4] 3 g[5] 3 g[4] 4 g[5] 4 r[0] 1 r[1] 1 r[0] 2 r[1] 2 r[0] 3 r[1] 3 r[0] 4 r[1] 4 r[2] 1 r[3] 1 r[2] 2 r[3] 2 r[2] 3 r[3] 3 r[2] 4 r[3] 4 r[4] 1 r[5] 1 r[4] 2 r[5] 2 r[4] 3 r[5] 3 r[4] 4 r[5] 4 clkp input dio: shl=h doi: shl=l d00p/n d01p/n d02p/n d10p/n d11p/n d12p/n d20p/n d21p/n d22p/n tsetup2 thold2 tsetup1 thold1 tsetup1 thold1 figure 6. rsds data timing diagram

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